1. Field
The present disclosure relates to a semiconductor integrated circuit, and more particularly, to a voltage measurement circuit for measuring an internal voltage of a chip.
2. Discussion of the Related Art
Generally, a power supply voltage for inside a chip employs an external power supply voltage input itself or a dropped or boosted voltage. Here, the dropped or boosted voltage can be obtained by dropping or boosting an external voltage to a predetermined voltage level through an internal voltage generating circuit. Since the internal voltage generated by the internal voltage generating circuit is used as an operating voltage within the chip, the internal voltage must be maintained at a stable voltage level.
FIG. 1 illustrates a conventional voltage measurement device for measuring an internal voltage. Referring to FIG. 1, the voltage measurement device includes a switching unit 120 connected to a pad 110, and an internal circuit block 140. The switching unit 120 connects an internal DC voltage line 130 to the pad 110 in response to a control signal CTRL. The pad 110 is an input pad for input of a signal for driving the internal circuit block 140, for example, an address signal or a command signal. In case of measuring an internal DC voltage, a voltage level of the internal DC voltage line 130 is applied to the pad 110.
However, the conventional voltage measurement device has following problems.
First, in case where the switching unit 120 is provided with a PMOS transistor 124, if the control signal (CTRL) is a high level (hereinafter, referred to as “H level”), the PMOS transistor 124 is turned off. At this point, a logic level input to the pad 110 is transferred to the internal circuit block 140. In the meantime, if a logic level input to the pad 110 is overshot up to “H level+Vtp”, where Vtp is the overshot voltage, the turned-off PMOS transistor 124 is turned on. Therefore, the overshot voltage level of the pad 110 is transferred to the internal DC voltage line 130, so that the internal DC voltage fluctuates. This results in a change of the internal DC voltage that must be maintained at a stable voltage level.
Second, in case where the switching unit 120 is provided with an NMOS transistor 122, if the control signal CTRL is a low level (hereinafter, referred to as “L level”), the NMOS transistor 122 is turned off. At this point, if a logic level inputted into the pad 110 is undershot down to “L level-Vtn”, where Vtn is the undershot voltage, the turned-off NMOS transistor 122 is turned on. Therefore, the undershot voltage level of the pad 110 is transferred to the internal DC voltage line 130, so that the internal DC voltage fluctuates.
Third, in case where the switching unit 120 is provided with an NMOS transistor 122 and a PMOS transistor 124, if the control signal CTRL is a low level, the NMOS transistor 122 and the PMOS transistor 124 are turned off. At this point, if a logic level input to the pad 110 is overshot up to “H level+Vtp” or undershot down to “L level-Vtn”, the turned-off NMOS transistor 122 and the turned-off PMOS transistor 124 are turned on. Therefore, the overshot or undershot voltage level of the pad 110 is transferred to the internal DC voltage line 130, so that the internal DC voltage fluctuates.
Therefore, it is necessary to provide a circuit for measuring the internal voltage through the input pad without changing the internal DC voltage.